Datasheet

74
XMEGA B [DATASHEET]
8291B–AVR–01/2013
6.8.2 CHnCTRL – Event Channel n Control register
Note: 1. Only available for CH0CTRL and CH2CTRL. These bits are reserved in CH1CTRL and CH3CTRL.
 Bit 7 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero
when this register is written.
 Bit 6:5 – QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals, where a valid index signal is recognized
and the counter index data event is given according to Table 6-5. These bits should only be set when a quadrature
encoder with a connected index signal is used.These bits are available only for CH0CTRL and CH2CTRL.
Table 6-5. QDIRM bit settings.
 Bit 4 – QDIEN: Quadrature Decode Index Enable
When this bit is set, the event channel will be used as a QDEC index source, and the index data event will be enabled.
This bit is available only for CH0CTRL and CH2CTRL.
 Bit 3 – QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
This bit is available only for CH0CTRL and CH2CTRL.
 Bit 2:0 – DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used, according to Table 6-6 on page 74. Events will be passed through to
the event channel only when the event source has been active and sampled with the same level for the number of
peripheral clock cycles defined by DIGFILT.
Bit 76543210
– QDIRM[1:0]
(1)
QDIEN
(1)
QDEN
(1)
DIGFILT[2:0]
– – – – – DIGFILT[2:0]
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0
QDIRM[1:0] Index Recognition State
0 0 {QDPH0, QDPH90} = 0b00
0 1 {QDPH0, QDPH90} = 0b01
1 0 {QDPH0, QDPH90} = 0b10
1 1 {QDPH0, QDPH90} = 0b11
Table 6-6. Digital filter coefficient values .
DIGFILT[2:0] Group Configuration Description
000 1SAMPLE One sample
001 2SAMPLES Two samples
010 3SAMPLES Three samples