Datasheet

62
XMEGA B [DATASHEET]
8291B–AVR–01/2013
5.14.9 SRCADDR1 – Channel Source Address 1
 Bit 7:0 – SRCADDR[15:8]: Channel Source Address byte 1
These bits hold byte 1 of the 24-bit source address.
5.14.10 SRCADDR2 – Channel Source Address 2
Reading and writing 24-bit values require special attention. For details, refer to “Accessing 24- and 32-bit Registers” on
page 13.
 Bit 7:0 – SRCADDR[23:16]: Channel Source Address byte 2
These bits hold byte 2 of the 24-bit source address.
5.14.11 DESTADDR0 – Channel Destination Address 0
DESTADDR0, DESTADDR1, and DESTADDR2 represent the 24-bit value DESTADDR, which is the DMA channel
destination address. DESTADDR2 holds the most significant byte in the register. DESTADDR may be automatically
incremented or decremented based on settings in the DESTDIR bits in “ADDRCTRL – Address Control register” on page
57.
 Bit 7:0 – DESTADDR[7:0]: Channel Destination Address byte 0
These bits hold byte 0 of the 24-bit source address.
Bit 76543210
+0x09 SRCADDR[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 00000
Bit 76543210
+0x0A SRCADDR[23:16]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x0C DESTADDR[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000