Datasheet

61
XMEGA B [DATASHEET]
8291B–AVR–01/2013
5.14.6 TRFCNTH – Channel Block Transfer Count register High
Reading and writing 16-bit values requires special attention. For details, refer to “Accessing 16-bit Registers” on page 13.
 Bit 7:0 – TRFCNT[15:8]: Channel n Block Transfer Count high byte
These bits hold the MSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trigger, DMA will be doing
0xFFFF transfers.
5.14.7 REPCNT – Repeat Counter register
REPCNT counts how many times a block transfer is performed. For each block transfer, this register will be
decremented.
When repeat mode is enabled (see REPEAT bit in “ADDRCTRL – Address Control register” on page 57), this register is
used to control when the transaction is complete. The counter is decremented after each block transfer if the DMA has to
serve a limited number of repeated block transfers. When repeat mode is enabled, the channel is disabled when
REPCNT reaches zero and the last block transfer is completed. Unlimited repeat is achieved by setting this register to
zero.
5.14.8 SRCADDR0 – Source Address 0
SRCADDR0, SRCADDR1, and SRCADDR2 represent the 24-bit value SRCADDR, which is the DMA channel source
address. SRCADDR2 is the most significant byte in the register. SRCADDR may be automatically incremented or
decremented based on settings in the SRCDIR bits in “ADDRCTRL – Address Control register” on page 57.
 Bit 7:0 – SRCADDR[7:0]: Channel Source Address byte 0
These bits hold byte 0 of the 24-bit source address.
Bit 76543210
+0x05 TRFCNT[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 00000
Bit 76543210
+0x06 REPCNT[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 000000
Bit 76543210
+0x08 SRCADDR[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0