Datasheet

60
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Note: 1. CC channel C and D triggers are available only for timer/counters 0.
The group configuration is the “base_offset;” for example, TCC1_CCA for the timer/counter C1 CC channel A the transfer
trigger.
5.14.5 TRFCNTL – Channel Block Transfer Count register Low
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT defines the number of bytes
in a block transfer. The value of TRFCNT is decremented after each byte read by the DMA channel. When TRFCNT
reaches zero, the register is reloaded with the last value written to it.
 Bit 7:0 – TRFCNT[7:0]: Channel n Block Transfer Count low byte
These bits hold the LSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trigger, DMA will be doing
0xFFFF transfers.
Table 5-9. DMA trigger source offset values for event system triggers.
TRGSRC Offset Value Group Configuration Description
+0x00 CH0 Event channel 0
+0x01 CH1 Event channel 1
+0x02 CH2 Event channel 2
Table 5-10. DMA trigger source offset values for timer/ counter triggers.
TRGSRC Offset Value Group Configuration Description
+0x00 OVF Overflow/underflow
+0x01 ERR Error
+0x02 CCA Compare or capture channel A
+0x03 CCB Compare or capture channel B
+0x04 CCC
(1)
Compare or capture channel C
+0x05 CCD
(1)
Compare or capture channel D
Table 5-11. DMA trigger source offset values for USART triggers.
TRGSRC Offset Value Group Configuration Description
0x00 RXC Receive complete
0x01 DRE Data register empty
Bit 76543210
+0x04 TRFCNT[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000