Datasheet

58
XMEGA B [DATASHEET]
8291B–AVR–01/2013
 Bit 5:4 – SRCDIR[1:0]: Channel Source Address Mode
These bits decide the DMA channel source address mode according to Table 5-5. These bits cannot be changed if the
channel is busy.
Table 5-5. DMA channel source address mode settings.
 Bit 3:2 – DESTRELOAD[1:0]: Channel Destination Address Reload
These bits decide the DMA channel destination address reload according to Table 5-6. These bits cannot be changed if
the channel is busy.
Table 5-6. DMA channel destination address reload settings
 Bit 1:0 – DESTDIR[1:0]: Channel Destination Address Mode
These bits decide the DMA channel destination address mode according to Table 5-7. These bits cannot be changed if
the channel is busy.
Table 5-7. DMA channel destination address mode settings
SRCDIR[1:0] Group Configuration Description
00 FIXED Fixed
01 INC Increment
10 DEC Decrement
11 - Reserved
DESTRELOAD[1:0] Group Configuration Description
00 NONE No reload performed.
01 BLOCK
DMA channel destination address register is reloaded with
initial value at end of each block transfer.
10 BURST
DMA channel destination address register is reloaded with
initial value at end of each burst transfer.
11 TRANSACTION
DMA channel destination address register is reloaded with
initial value at end of each transaction.
DESTDIR[1:0] Group Configuration Description
00 FIXED Fixed
01 INC Increment
10 DEC Decrement
11 - Reserved