Datasheet

XMEGA B [DATASHEET]

8291B–AVR–01/2013

 Bit 6 – CHPEND: Channel Pending

If a block transfer is pending on the DMA channel, the CHPEND flag will be read as one. This flag is automatically

cleared when the transfer starts or if the transfer is aborted.

 Bit 5 – ERRIF: Error Interrupt Flag

If an error condition is detected on the DMA channel, the ERRIF flag will be set and the optional interrupt is generated.

Since the DMA channel error interrupt shares the interrupt address with the DMA channel n transaction complete

interrupt, ERRIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing a one to this

location.

 Bit 4 – TRNIF: Channel n Transaction Complete Interrupt Flag

When a transaction on the DMA channel has been completed, the TRNIF flag will be set and the optional interrupt is

generated. When repeat is not enabled, the transaction is complete and TRNIFR is set after the block transfer. When

unlimited repeat is enabled, TRNIF is also set after each block transfer.

Since the DMA channel transaction n complete interrupt shares the interrupt address with the DMA channel error

interrupt, TRNIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing a one to this

location.

 Bit 3:2 – ERRINTLVL[1:0]: Channel Error Interrupt Level

These bits enable the interrupt for DMA channel transfer errors and select the interrupt level, as described in “Interrupts

and Programmable Multilevel Interrupt Controller” on page 118. The enabled interrupt will trigger for the conditions when

ERRIF is set.

 Bit 1:0 – TRNINTLVL[1:0]: Channel Transaction Complete Interrupt Level

These bits enable the interrupt for DMA channel transaction completes and select the interrupt level, as described in

“Interrupts and Programmable Multilevel Interrupt Controller” on page 118. The enabled interrupt will trigger for the

conditions when TRNIF is set.

5.14.3 ADDRCTRL – Address Control register

 Bit 7:6 – SRCRELOAD[1:0]: Channel Source Address Reload

These bits decide the DMA channel source address reload according to Table 5-4. A write to these bits is ignored while

the channel is busy.

Table 5-4. DMA channel source address reload settings

Bit 76543210

+0x02 SRCRELOAD[1:0] SRCDIR[1:0] DESTRELOAD[1:0] DESTDIR[1:0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0000000

SRCRELOAD[1:0] Group Configuration Description

00 NONE No reload performed.

01 BLOCK

DMA source address register is reloaded with initial value at end

of each block transfer.

10 BURST

DMA source address register is reloaded with initial value at end

of each burst transfer.

11 TRANSACTION

DMA source address register is reloaded with initial value at end

of each transaction.