Datasheet

XMEGA B [DATASHEET]

8291B–AVR–01/2013

 Bit 1:0 – BURSTLEN[1:0]: Burst Mode

These bits decide the DMA channel burst mode according to Table 5-2 on page 56. These bits cannot be changed if the

channel is busy.

Table 5-2. DMA channel burst mode

Table 5-3. Summary of triggers, transaction complete flag and channel disable according to DMA channel

configuration.

5.14.2 CTRLB – Control register B

 Bit 7 – CHBUSY: Channel Busy

When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one. This flag is automatically

cleared when the DMA channel is disabled, when the channel transaction complete interrupt flag is set or when the

channel error interrupt flag is set.

BURSTLEN[1:0] Group Configuration Description

00 1BYTE 1 byte burst mode

01 2BYTE 2 bytes burst mode

10 4BYTE 4 bytes burst mode

11 8BYTE 8 bytes burst mode

REPEAT SINGLE REPCNT Trigger Flag Set After Channel Disabled After

0 0 0 Block 1 block 1 block

0 0 1 Block 1 block 1 block

0 0 n > 1 Block 1 block 1 block

0 1 0 BURSTLEN 1 block 1 block

0 1 1 BURSTLEN 1 block 1 block

0 1 n > 1 BURSTLEN 1 block 1 block

1 0 0 Block Each block Each block

1 0 1 Transaction 1 block 1 block

1 0 n > 1 Transaction n blocks n blocks

1 1 0 BURSTLEN Each block Never

1 1 1 BURSTLEN 1 block 1 block

1 1 n > 1 BURSTLEN n blocks n blocks

Bit 76543210

+0x01 CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0]

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0