Datasheet

55
XMEGA B [DATASHEET]
8291B–AVR–01/2013
5.13.5 TEMPH – Temporary Register High
 Bit 7:0 – TEMP[15:8]: Temporary Register
This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of the 24-bit register is stored
when it is written by the CPU. Byte 2 of the 24-bit register is stored here when byte 1 is read by the CPU. This register
can also be read and written from the user software.
Reading and writing 24-bit registers requires special attention. For details, refer to “Accessing 16-bit Registers” on page
13.
5.14 Register Description – DMA Channel
5.14.1 CTRLA – Control register A
 Bit 7 – ENABLE: Channel Enable
Setting this bit enables the DMA channel. This bit is automatically cleared when the transaction is completed. If the DMA
channel is enabled and this bit is written to zero, the CHEN bit is not cleared until the internal transfer buffer is empty and
the DMA transfer is aborted.
 Bit 6 – RESET: Software Reset
Setting this bit will reset the DMA channel. It can only be set when the DMA channel is disabled (CHEN = 0). Writing a
one to this bit will be ignored as long as the channel is enabled (CHEN=1). This bit is automatically cleared when reset is
completed.
 Bit 5 – REPEAT: Repeat Mode
Setting this bit enables the repeat mode. In repeat mode, this bit is cleared by hardware at the beginning of the last block
transfer. The REPCNT register should be configured before setting the REPEAT bit.
 Bit 4 – TRFREQ: Transfer Request
Setting this bit requests a data transfer on the DMA channel. This bit is automatically cleared at the beginning of the data
transfer. Writing this bit does not have any effect unless the channel is enabled.
 Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
 Bit 2 – SINGLE: Single-Shot Data transfer
Setting this bit enables the single-shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the
transfer trigger. A write to this bit will be ignored while the channel is enabled.
Bit 76543210
+0x07 TEMP[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
+0x00 ENABLE RESET REPEAT TRFREQ
– SINGLE BURSTLEN[1:0]
Read/Write R/W R/W R/W R/W R R/W R/W R/W
Initial Value 0 0 000000