Datasheet

54
XMEGA B [DATASHEET]
8291B–AVR–01/2013
 Bit 5:4 – CHnERRIF[1:0]: Channel n Error Interrupt Flag
If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one to this bit location will
clear the flag.
 Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 1:0 – CHnTRNFIF[1:0]: Channel n Transaction Complete Interrupt Flag
When a transaction on channel n has been completed, the CHnTRFIF flag will be set. If unlimited repeat count is
enabled, this flag is read as one after each block transfer. Writing a one to this bit location will clear the flag.
5.13.3 STATUS – Status register
 Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 5:4 – CHnBUSY[1:0]: Channel Busy
When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is automatically cleared when
the DMA channel is disabled, when the channel n transaction complete interrupt flag is set, or if the DMA channel n error
interrupt flag is set.
 Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written
 Bit 1:0 – CHnPEND[1:0]: Channel Pending
If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This flag is automatically cleared
when the block transfer starts or if the transfer is aborted.
5.13.4 TEMPL – Temporary register Low
 Bit 7:0 – TEMP[7:0]: Temporary register 0
This register is used when reading 16- and 24-bit registers in the DMA controller. Byte 1 of the 16/24-bit register is stored
here when it is written by the CPU. Byte 1 of the 16/24-bit register is stored when byte 0 is read by the CPU. This register
can also be read and written from the user software.
Reading and writing 16- and 24-bit registers requires special attention. For details, refer to “Accessing 16-bit Registers”
on page 13.
Bit 76543210
+0x04
– – CH1BUSY CH0BUSY – – CH1PEND CH0PEND
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x06 TEMP[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0