Datasheet

52
XMEGA B [DATASHEET]
8291B–AVR–01/2013
5.9 Error detection
The DMA controller can detect erroneous operation. Error conditions are detected individually for each DMA channel,
and the error conditions are:
 Write to memory mapped EEPROM locations
 Reading EEPROM when the EEPROM is off (sleep entered)
 DMA controller or a busy channel is disabled in software during a transfer
5.10 Software Reset
Both the DMA controller and a DMA channel can be reset from the user software. When the DMA controller is reset, all
registers associated with the DMA controller, including channels, are cleared. A software reset can be done only when
the DMA controller is disabled.
When a DMA channel is reset, all registers associated with the DMA channel are cleared. A software reset can be done
only when the DMA channel is disabled.
5.11 Protection
In order to ensure safe operation, some of the channel registers are protected during a transaction. When the DMA
channel busy flag (CHnBUSY) is set for a channel, the user can modify only the following registers and bits:
 CTRL register
 INTFLAGS register
 TEMP registers
 CHEN, CHRST, TRFREQ, and REPEAT bits of the channel CTRL register
 TRIGSRC register
5.12 Interrupts
The DMA controller can generate interrupts when an error is detected on a DMA channel or when a transaction is
complete for a DMA channel. Each DMA channel has a separate interrupt vector, and there are different interrupt flags
for error and transaction complete.
If repeat is not enabled, the transaction complete flag is set at the end of the block transfer. If unlimited repeat is enabled,
the transaction complete flag is also set at the end of each block transfer.