Datasheet

44
XMEGA B [DATASHEET]
8291B–AVR–01/2013
4.18.7 ANAINIT – Analog Initialization register
 Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 3:2 / 1:0 – STARTUPDLYx: Start-Up Delay
Setting these bits enables sequential start of the internal components used for the ADC, DAC, and analog comparator
with the main input/output connected to that port. When this is done, the internal components, such as voltage reference
and bias currents, are started sequentially when the module is enabled. This reduces the peak current consumption
during startup of the module. For maximum effect, the start-up delay should be set so that it is larger than 0.5μs.
Table 4-13. Analog start-up delay.
4.18.8 EVSYSLOCK – Event System Lock register
 Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 0 – EVSYS0LOCK:
Setting this bit will lock all registers in the event system related to event channels 0 to 3 for further modification. The
following registers in the event system are locked: CH0MUX, CH0CTRL, CH1MUX, CH1CTRL, CH2MUX, CH2CTRL,
CH3MUX, and CH3CTRL. This bit is protected by the configuration change protection mechanism. For details, refer to
“Configuration Change Protection” on page 14.
Bit 76543210
+0x07
– – – – STARTUPDLYB[1:0] STARTUPDLYA[1:0]
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
STARTUPDLYx Group Configuration Description
00 NONE Direct startup
11 2CLK 2 * CLK
PER
10 8CLK 8 * CLK
PER
11 32CLK 32 * CLK
PER
Bit 7 6 5 4 3 2 1 0
+0x08
– – – – – – – EVSYS0LOCK
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0