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Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller CBGA 100 (9x9) 8/16-Bit 32 MHz I/O number 53
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XMEGA B [DATASHEET]
8291B–AVR–01/2013
33. Datasheet Revision History
Please note that the referring page numbers in this section are referring to this document. The referring revision in this
section are referring to the document revision.
33.1 8291B – 01/2013
1. Added XMEGA B feature overview inTable 2-1 on page 5.
2. References to Calibration Row updated to Production Signature Row for consistency.
3. Added reference to “NVM Flash Commands” on page 382 in “Production Signature Row” on page 22.
4. Updated “LOCKBITS – Lock Bits register” on page 30. Description of Bit[1:0] updated and added a table note.
5. Title of Table 4-12 on page 35 changed to “Lock bit protection mode.”
6. Updated “TRIGSRC – Trigger Source” on page 59. The description Bit[7:0] updated.
7 Updated description of “CHnCTRL – Event Channel n Control register” on page 74.
8. Updated the formula of COMP register in “DFLL 2MHz and DFLL 32MHz” on page 82.
9. Updated Table 9-2 on page 108, the “Programmable BODLEVEL setting.”
10. Table note added to the Table 10-1 on page 115.
11. Table note added to the Table 10-2 on page 116.
12. Updated “Port Interrupt” on page 132.
13. Updated Table 12-3 on page 133. “Both edge” replaced by “Any edge”.
14. Updated “Port Event” on page 133.
15. Updated Table 12-10 on page 145, and Table 12-11 on page 146.
16. Updated “Event Action Controlled Operation” on page 156.
17. Updated Figure 13-10 on page 158. CH7MUX changed to CHnMUX.
18 Updated Table 13-2 in “DMA Support” on page 163.
19. Updated Table 14-3 on page 182. CMD changed to BYTEM[1:0]
20. Updated “Clock Domains” on page 202.
21. Updated description in “For Output Endpoints” on page 216.
22. Updated both formula of “BAUD – Baud Rate register” on page 250
23. Updated “DATA – Data register” on page 251. Added the description of ADDR[7:1] and ADDR[0]
24. Updated the formula in “Fractional Baud Rate Generation” on page 274.
25. Updated Figure 21-9 on page 275, the “Fractional baud rate example.”
26. Added Table 21-5 on page 275, the “USART baud rate.”
27. Updated “ADC Input Model” on page 334.