Datasheet

375
XMEGA B [DATASHEET]
8291B–AVR–01/2013
29.6 Register Description – PDI Control and Status Registers
The PDI control and status registers are accessible in the PDI control and status register space (CSRS) using the LDCS
and STCS instructions. The CSRS contains registers directly involved in configuration and status monitoring of the PDI
itself.
29.6.1 STATUS – Status register
 Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 1 – NVMEN: Nonvolatile Memory Enable
This status bit is set when the key signalling enables the NVM programming interface. The external programmer can poll
this bit to verify successful enabling. Writing the NVMEN bit disables the NVM interface.
 Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
29.6.2 RESET – Reset register
 Bit 7:0 – RESET[7:0]: Reset Signature
When the reset signature, 0x59, is written to RESET, the device is forced into reset. The device is kept in reset until
RESET is written with a data value different from the reset signature. Reading the lsb will return the status of the reset.
The seven msbs will always return the value 0x00, regardless of whether the device is in reset or not.
29.6.3 CTRL – Control register
 Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2:0 – GUARDTIME[2:0]: Guard Time
These bits specify the number of IDLE bits of guard time that are inserted in between PDI reception and transmission
direction changes. The default guard time is 128 IDLE bits, and the available settings are shown in Table 29-1 on page
376. In order to speed up the communication, the guard time should be set to the lowest safe configuration accepted. No
guard time is inserted when switching from TX to RX mode.
Bit 76543210
+0x00
– – – – – – NVMEN –
Read/Write R RRRRRR/WR
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x01 RESET[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 00000
Bit 76543210
+0x02
– – – – – GUARDTIME[2:0]
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0