Datasheet

367
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 29-1. The PDI and PDI physical layers and closely related modules (grey).
29.3 PDI Physical
The PDI physical layer handles the low-level serial communication. It uses a bidirectional, half-duplex, synchronous
serial receiver and transmitter (just as a USART in USRT mode). The physical layer includes start-of-frame detection,
frame error detection, parity generation, parity error detection, and collision detection.
In addition to PDI_CLK and PDI_DATA, the PDI_DATA pin has an internal pull resistor, V
CC
and GND must be
connected between the External Programmer/debugger and the device. Figure 29-2 on page 367 shows a typical
connection.
Figure 29-2. PDI connection.
The remainder of this section is intended for use only by third parties developing programmers or programming support
for Atmel AVR XMEGA devices.
29.3.1 Enabling
The PDI physical layer must be enabled before use. This is done by first forcing the PDI_DATA line high for a period
longer than the equivalent external reset minimum pulse width (refer to device datasheet for external reset pulse width
data). This will disable the
RESET functionality of the Reset pin, if not already disabled by the fuse settings.
Next, continue to keep the PDI_DATA line high for 16 PDI_CLK cycles. The first PDI_CLK cycle must start no later than
100μs after the
RESET functionality of the Reset pin is disabled. If this does not occur in time, the enabling procedure
must start over again. The enable sequence is shown in Figure 29-3 on page 368.
PDI
Controller
PDI Physical
(physical layer)
OCD
NVM
Controller
Program and Debug Interface (PDI)
PDI_CLK
PDI_DATA
NVM
Memories
Internal InterfacesPDIBUS