Datasheet

362
XMEGA B [DATASHEET]
8291B–AVR–01/2013
The active states are:
 Capture DR: Loads a zero into the bypass register
 Shift DR: The bypass register cell between TDI and TDO is shifted
28.4.5 CLAMP; 0x4
CLAMP is an optional instruction that allows the state of the input/output pins to be determined from the preloaded output
latches. The instruction allows static pin values to be applied via the boundary scan registers while bypassing these
registers in the scan path, efficiently shortening the total length of the serial test path. The bypass register is selected as
the data register.
The active states are:
 Capture DR: Loads a zero into the bypass register
 Shift DR: The bypass register cell between TDI and TDO is shifted
28.4.6 HIGHZ; 0x5
HIGHZ is an optional instruction for putting all outputs in an inactive drive state (e.g., high impedance). The bypass
register is selected as the data register.
The active states are:
 Capture DR: Loads a zero into the bypass register
 Shift DR: The bypass register cell between TDI and TDO is shifted
28.4.7 PDICOM; 0x7
PDICOM is an AVR XMEGA specific instruction for using the JTAG TAP as an alternative interface to the PDI.
The active states are:
 Capture DR: Parallel data from the PDI are sampled into the PDICOM data register
 Shift DR: The PDICOM data register is shifted by the TCK input
 Update DR: Commands or operands are parallel-latched from the PDICOM data register into the PDI
28.5 Boundary Scan Chain
The boundary scan chain has the capability of driving and observing the logic levels on the I/O pins. To ensure a
predictable device behavior during and after the EXTEST, CLAMP, and HIGHZ instructions, the device is automatically
put in reset. During active reset, the external oscillators, analog modules, and non-default port pin settings (like pull-
up/down, bus-keeper, wired-AND/OR) are disabled. It should be noted that the current device and port pin state are
unaffected by the SAMPLE and PRELOAD instructions.
28.5.1 Scanning the Port Pins
Figure 28-2 on page 363 shows the boundary scan cell used for all the bidirectional port pins. This cell is able to control
and observe both pin direction and pin value via a two-stage shift register. When no alternate port function is present,
output control corresponds to the DIR register value, output data corresponds to the OUT register value, and input data
corresponds to the IN register value (tapped before the input inverter and input synchronizer). Mode represents either an
active CLAMP or EXTEST instruction, while shift DR is set when the TAP controller is in its shift DR state.