Datasheet

360
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 28-1. TAP controller state diagram.
The TAP controller is a 16-state, finite state machine that controls the operation of the boundary scan circuitry. The state
transitions shown in Figure 28-1 depend on the signal present on TMS (shown adjacent to each state transition) at the
time of the rising edge on TCK. The initial state after a power-on reset is the test logic reset state.
Assuming the present state is run test/idle, a typical scenario for using the JTAG interface is:
 At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the shift instruction register, or
shift IR, state. While in this state, shift the four bits of the JTAG instruction into the JTAG instruction register from
the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 lsbs in order to
remain in the shift IR state. The msb of the instruction is shifted in when this state is left by setting TMS high. While
the instruction is shifted in from the TDI pin, the captured IR state, 0x01, is shifted out on the TDO pin. The JTAG
instruction selects a particular data register as the path between TDI and TDO and controls the circuitry
surrounding the selected data register
 Apply the TMS sequence 1, 1, 0 to reenter the run test/idle state. The instruction is latched onto the parallel output
from the shift register path in the update IR state. The exit IR, pause IR, and exit2 IR states are used only for
navigating the state machine
 At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the shift data register, or shift DR,
state. While in this state, upload the selected data register (selected by the present JTAG instruction in the JTAG
instruction register) from the TDI input at the rising edge of TCK. In order to remain in the shift DR state, the TMS
input must be held low during the input of all bits except the msb. The msb of the data is shifted in when this state
is left by setting TMS high. While the data register is shifted in from the TDI pin, the parallel inputs to the data
register captured in the capture DR state are shifted out on the TDO pin
 Apply the TMS sequence 1, 1, 0 to reenter the run test/idle state. If the selected data register has a latched parallel
output, the latching takes place in the update DR state. The exit DR, pause DR, and exit2 DR states are used only
for navigating the state machine.