Datasheet

353
XMEGA B [DATASHEET]
8291B–AVR–01/2013
27.8 Register Description
27.8.1 ACnCTRL – Analog Comparator n Control register
 Bit 7:6 – INTMODE[1:0]: Interrupt Modes
These bits configure the interrupt mode for analog comparator n according to Table 27-1.
Table 27-1. Interrupt settings.
 Bit 5:4 – INTLVL[1:0]: Interrupt Level
These bits enable the analog comparator n interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 101. The enabled interrupt will trigger according to the INTMODE
setting.
 Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
 Bit 2:1 – HYSMODE[1:0]: Hysteresis Mode Select
These bits select the hysteresis mode according to Table 27-2. For details on actual hysteresis levels, refer to the device
datasheet.
Table 27-2. Hysteresis settings.
 Bit 0 – ENABLE: Enable
Setting this bit enables analog comparator n.
Bit 7 6 5 4 3 2 1 0
+0x00 / +0x01 INTMODE[1:0] INTLVL[1:0]
– HYSMODE[2:0] ENABLE
Read/Write R/W R/W R/W R/W R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
INTMODE[1:0] Group Configuration Description
00 BOTHEDGES Comparator interrupt or event on output toggle
01 – Reserved
10 FALLING Comparator interrupt or event on falling output edge
11 RISING Comparator interrupt or event on rising output edge
HYSMODE[1:0] Group Configuration Description
00 NO No hysteresis
01 SMALL Small hysteresis
10 LARGE Large hysteresis
11 – Reserved