Datasheet

343
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Table 26-7. ADC gain factor
 Bit 1:0 – INPUTMODE[1:0]: Channel Input Mode
These bits define the channel mode.
Table 26-8. Channel input modes, CONVMODE=0 (unsigned mode).
Table 26-9. Channel input modes, CONVMODE=1 (singed mode).
26.16.2 MUXCTRL – MUX Control registers
The MUXCTRL register defines the input source for the channel.
 Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
GAIN[2:0] Group Configuration Gain Factor
000 1X 1x
001 2X 2x
010 4X 4x
011 8X 8x
100 16X 16x
101 32X 32x
110 64X 64x
111 DIV2 ½x
INPUTMODE[1:0] Group Configuration Description
00 INTERNAL Internal positive input signal
01 SINGLEENDED Single-ended positive input signal
10 – Reserved
11 – Reserved
INPUTMODE[1:0] Group Configuration Description
00 INTERNAL Internal positive input signal
01 SINGLEENDED Single-ended positive input signal
10 DIFF Differential input signal
11 DIFFWGAIN Differential input signal with gain
Bit 7 6543210
+0x01
– MUXPOS[3:0] MUXNEG[2:0]
Read/Write R R/W R/W R/W R/W R R/W R/W
Initial Value 0 0000000