Datasheet

342
XMEGA B [DATASHEET]
8291B–AVR–01/2013
26.15.13 CMPH – Compare register High
The CMPH and CMPL register pair represents the 16-bit value, CMP. For details on reading and writing 16-bit registers,
refer to “Accessing 16-bit Registers” on page 11.
 Bit 7:0 – CMP[15:0]: Compare Value High byte
These are the eight msbs of the 16-bit ADC compare value. In signed mode, the number representation is 2's
complement, and the msb is the sign bit.
26.15.14 CMPL – Compare register Low
 Bit 7:0 – CMP[7:0]: Compare Value Low byte
These are the eight lsbs of the 16-bit ADC compare value. In signed mode, the number representation is 2's
complement.
26.16 Register Description - ADC Channel
26.16.1 CTRL – Control Register
 Bit 7 – START: START Conversion on Channel
Setting this bit will start a conversion on the channel. The bit is cleared by hardware when the conversion has started.
Setting this bit when it already is set will have no effect. Writing or reading this bit is equivalent to writing the
CH[3:0]START bits in “CTRLA – Control register A” on page 336.
 Bit 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 4:2 – GAIN[2:0]: Gain Factor
These bits define the gain factor for the ADC gain stage.
See Table 26-7 on page 343. Gain is valid only with certain MUX settings. See “MUXCTRL – MUX Control registers” on
page 343.
Bit 76543210
+0x19 CMP[15:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 000000
Bit 76543210
+0x18 CMP[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
+0x00 START
– – GAIN[2:0] INPUTMODE[1:0]
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 000000