Datasheet

341
XMEGA B [DATASHEET]
8291B–AVR–01/2013
26.15.11CH0RESH – Channel 0 Result register High
The CH0RESL and CH0RESH register pair represents the 16-bit value, CH0RES. For details on reading 16-bit registers,
refer to “Accessing 16-bit Registers” on page 11.
26.15.11.1 12-bit Mode, Left Adjusted
 Bit 7:0 – CHRES[11:4]: Channel Result High byte
These are the eight msbs of the 12-bit ADC result.
26.15.11.2 12-bit Mode, Right Adjusted
 Bit 7:4 – Reserved
These bits will in practice be the extension of the sign bit, CHRES11, when the ADC works in differential mode, and set
to zero when the ADC works in signed mode.
 Bit 3:0 – CHRES[11:8]: Channel Result High byte
These are the four msbs of the 12-bit ADC result.
26.15.11.3 8-bit Mode
 Bit 7:0 – Reserved
These bits will in practice be the extension of the sign bit, CHRES7, when the ADC works in signed mode, and set to zero
when the ADC works in single-ended mode.
26.15.12 CH0RESL – Channel 0 Result register Low
26.15.12.1 12-/8-bit Mode
 Bit 7:0 – CHRES[7:0]: Channel Result Low byte
These are the eight lsbs of the ADC result.
26.15.12.2 12-bit Mode, Left Adjusted
 Bit 7:4 – CHRES[3:0]: Channel Result Low byte
These are the four lsbs of the 12-bit ADC result.
 Bit 3:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 76543210
12-bit, left CHRES[11:4]
12-bit, right
– – – – CHRES[11:8]
8-bit
– – – – – – – –
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
12-/8-bit,
right
CHRES[7:0]
12-bit, left CHRES[3:0]
– – – –
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0