Datasheet

339
XMEGA B [DATASHEET]
8291B–AVR–01/2013
26.15.5 PRESCALER – Clock Prescaler register
 Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2:0 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock according to Table 26-6.
Table 26-6. ADC prescaler settings.
26.15.6 INTFLAGS – Interrupt Flag register
 Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 0 – CH0IF: Interrupt Flags
This flag is set when the ADC conversion is complete. If the ADC is configured for compare mode, the interrupt flag will
be set if the compare condition is met. CH0IF is automatically cleared when the ADC interrupt vector is executed. The
flag can also be cleared by writing a one to its bit location.
101 – Reserved
110 SYNCSWEEP The ADC is flushed and restarted for accurate timing
111 – Reserved
EVACT[2:0] Group Configuration Event Input Operation Mode
Bit 7 6 5 4 3 2 1 0
+0x04
– – – – – PRESCALER[2:0]
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
PRESCALER[2:0] Group Configuration Peripheral Clock Division Factor
000 DIV4 4
001 DIV8 8
010 DIV16 16
011 DIV32 32
100 DIV64 64
101 DIV128 128
110 DIV256 256
111 DIV512 512
Bit 76543210
+0x06
– – – – – – – CH0IF
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0