Datasheet

336
XMEGA B [DATASHEET]
8291B–AVR–01/2013
26.15 Register Description – ADC
26.15.1 CTRLA – Control register A
 Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2 – CH0START: Channel Start Single Conversion
Setting this bit will start an ADC conversion. Bit is cleared by hardware when the conversion has started. Writing this bit
is equivalent to writing the START bits inside the ADC channel register.
 Bit 1 – FLUSH: Pipeline Flush
Setting this bit will flush the ADC. When this is done, the ADC clock is restarted on the next peripheral clock edge, and
the conversion in progress is aborted and lost.
After the flush and the ADC clock restart, the ADC will resume where it left off; i.e., if any conversions were pending,
these will enter the ADC and complete.
 Bit 0 – ENABLE: Enable
Setting this bit enables the ADC.
26.15.2 CTRLB – ADC Control register B
 Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
 Bit 6:5 – CURRLIMIT[1:0]: Current Limitation
These bits can be used to limit the current consumption of the ADC by reducing the maximum ADC sample rate. The
available settings are shown in Table 26-1. The indicated current limitations are nominal values. Refer to the device
datasheet for actual current limitation for each setting.
Table 26-1. ADC current limitations.
Bit 76543 2 10
+0x00
– – – – – CH0START FLUSH ENABLE
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0000 0 00
Bit 7 6 5 4 3 2 1 0
+0x01
– CURRLIMIT[1:0] CONVMODE FREERUN RESOLUTION[1:0] –
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0
CURRLIMIT[1:0] Group Configuration Description
00 NO No limit
01 LOW Low current limit, max. sampling rate 225kSPS
10 MED Medium current limit, max. sampling rate 150kSPS
11 HIGH High current limit, max. sampling rate 75kSPS