Datasheet

333
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 26-14.ADC timing for one single conversion with increased sampling time (SAMPVAL = 6).
26.9.2 Single Conversion with Gain
Figure 26-15 on page 333 to Figure 26-17 on page 334 show the ADC timing for one single conversion with various gain
settings. As seen in the “Overview” on page 325, the gain stage is built into the ADC. Gain is achieved by running the
signal through a pipeline stage without converting. Compared to a conversion without gain, each gain multiplication of 2
adds one half ADC clock cycle propagation delay.
Figure 26-15.ADC timing for one single conversion with 2x gain.
Figure 26-16.ADC timing for one single conversion with 8x gain.
CONVERTING BIT
START
IF
ADC SAMPLE
msb
10
9
8 7
6
5 4
3 2
1
lsb
clk
ADC
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10
CONVERTING BIT
START
IF
ADC SAMPLE
AMPLIFY
msb
10
9
8
7 6 5 4 3 2 1 lsb
clk
ADC
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CONVERTING BIT
START
IF
ADC SAMPLE
AMPLIFY
msb 10 9
8
7 6 5 4 3 2 1 lsb
clk
ADC
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