Datasheet

315
XMEGA B [DATASHEET]
8291B–AVR–01/2013
 Bits 1:0 – DUTY[1:0]: Duty Select
(1)
The DUTY bit-field defines the duty cycle. Common pins that are not used will be driven to ground. The different duty
selections are shown in Table 25-9.
Table 25-9. Duty cycle.
Note: 1. Refer to specific device datasheet for duty cycles availability (linked to the number of available common terminals).
25.5.3 CTRLC – Control register C
 Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bits 5:0 – PMSK[5:0]: LCD Port Mask
The PMSK bit-field defines the number of port pins to be used as segment drivers. The unused pins will be driven to
ground except the 16 highest pins which become GPIO's.
25.5.4 INTCTRL – Interrupt Control register
 Bits 7:3 – XIME[4:0]: eXtended Interrupt Mode Enable
XIME bit-field defines the number of frames to be completed for one interrupt period.
Interrupt Period = ( ( XIME[4:0] + 1 ) x 2
LPWAV
) frames
 For default waveforms, the FCIF flag is generated every XIME[4:0] + 1 frames. The range is 1 up to 32 frames.
 For low power waveforms requiring 2 subsequent frames, the FCIF flag is generated every
2 x ( XIME[4:0] + 1 ) frames. The range is 2 up to 64 frames.
Note: This extended interrupt mode generates a stable time base from the frame rate.
 Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
DUTY[1:0] Duty Bias COM pins Used
0 0 1/4 1/3 COM[0:3]
0 1 Static Static COM0
1 0 1/2 1/3 COM[0:1]
1 1 1/3 1/3 COM[0:2]
Bit 76543210
+0x02
– – PMSK[5:0]
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x03 XIME[4:0]
– FCINTLVL[1:0]
Read/Write R/W R/W R/W R/W R/W R R/W R/W
Initial Value 0 0 000000