Datasheet

314
XMEGA B [DATASHEET]
8291B–AVR–01/2013
 Bit 6:4 – CLKDIV[2:0]: LCD Clock Division
The CLKDIV bit-field defines the division ratio in the clock divider. The various selections are shown in Table 25-7. This
Clock Divider gives extra flexibility in frame rate setting.
Frame rate equation:
Where:
N = prescaler divider (8 or 16).
K = 8 for 1/4, 1/2 and static duty.
K = 6 for 1/3 duty.
Table 25-7. LCD clock divider (1/4 dyty).
Note that when using 1/3 duty, the frame rate is increased by 33% compared to the values listed above.
Table 25-8. Example of frame rate calculation.
 Bit 3 – LPWAV: Low Power Waveform
When LPWAV is written to one, the low power waveform is outputted on LCD pins, otherwise the standard waveform is
outputted. If this bit is modified during display operation the change takes place at the beginning of the next frame. (For
more details see “Low Power Waveform” on page 307).
 Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
CLKDIV[2:0] Divided by
Frame Rate (1/4 Duty)
F(clk
LCD
) = 32 kHz F(clk
LCD
) = 32768 Hz
N=8 N=16 N=8 N=16
000 1 500 Hz 250 Hz 512 Hz 256 Hz
001 2 250 Hz 125 Hz 256 Hz 128 Hz
010 3 166.667 Hz 83.333 Hz 170.667 Hz 85.333 Hz
011 4 125 Hz 62.5 Hz 128 Hz 64 Hz
100 5 100 Hz 50 Hz 102.4 Hz 51.2 Hz
101 6 83.333 Hz 41.667 Hz 85.333 Hz 42.667 Hz
110 7 71.429 Hz 35.714 Hz 73.143 Hz 36.671 Hz
111 8 62.5 Hz 31.25 Hz 64 Hz 32 Hz
clk
LCD
Duty K PRESC N CLKDIV[2:0] Frame rate
32.768kHz Static 8 1 16 4 32768 / ( 8 x 16 x ( 1 + 4 ) ) = 51.2Hz
32.768kHz 1/2 8 1 16 4 32768 / ( 8 x 16 x ( 1 + 4 ) ) = 51.2Hz
32.768kHz 1/3 6 1 16 4 32768 / ( 6 x 16 x ( 1 + 4 ) ) = 68.267Hz
32.768kHz 1/4 8 1 16 4 32768 / ( 8 x 16 x ( 1 + 4 ) ) = 51.2Hz
FrameRate
F clk
LCD

KN 1 CLKDIV+

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