Datasheet

312
XMEGA B [DATASHEET]
8291B–AVR–01/2013
25.5 Register Description – LCD
25.5.1 CTRLA – Control register A
 Bit 7 – ENABLE: LCD Enable
Writing this bit to one enables the LCD. By writing it to zero, the LCD is turned “OFF” immediately. Turning the LCD
“OFF” while driving a display, drives the output to ground to discharge the display (apart from segment terminals which
will be controlled by GPIO settings).
 Bit 6 – XBIAS: External Bias Generation
When this bit is set, the LCD buffers which drive the intermediate voltage levels are turned “OFF”. When XBIAS is “OFF”,
an external source for V
LCD
is necessary.
 Bit 5 – DATLCK: Data Register Lock
Writing this bit to one freezes the Shadow Display Memory. If the Display Memory is modified, the Shadow Display
Memory is locked and the display remains unchanged. When the bit is cleared, the Shadow Display Memory is updated
when a new frame starts (see Figure 25-2 on page 305).
 Bit 4 – COMSWP: Common Terminal Bus Swap
(1)
Writing this bit to one inverts the order of the common terminal bus (COM[3:0]). The common terminals disabled by
DUTY[1:0] are also affected (see Table 25-4).
Table 25-4. Common terminal bus reverse.
Note: 1. Refer to specific device datasheet for availability of this feature.
 Bit 3 – SEGSWP: Segment Terminal Bus Swap
(1)
Writing this bit to one inverts completely the order of the segment terminal bus (SEG[39:0]). The segment terminals un-
selected by PMSK[5:0] are also affected (see Table 25-5 on page 313).
Bit 76543210
+0x00 ENABLE XBIAS DATLCK COMSWP SEGSWP CLRDT SEGON BLANK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
DUTY[1:0] Number of COM COMSWP = 0 COMSWP = 1
00 4 COM3,COM2,COM1,COM0 COM0,COM1,COM2,COM3
01 1 –, –, –, COM0 COM0, –, –, –
10 2 –, –, COM1, COM0 COM0, COM1, –, –
11 3 –, COM2, COM1, COM0 COM0, COM1, COM2, –