Datasheet

301
XMEGA B [DATASHEET]
8291B–AVR–01/2013
24.7.2 STATUS – Status register
 Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 1 – ZERO: Checksum Zero
This flag is set if the CHECKSUM is zero when the CRC generation is complete. It is automatically cleared when a new
CRC source is selected.
When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum shold
be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little endian) to the
data, the final result in the checksum register will be zero.
See the description of CHECKSUM to read out different versions of the CHECKSUM.
 Bit 0 – BUSY: Busy
This flag is read as one when a source configuration is selected and as long as the source is using the CRC module. If
the I/O interface is selected as the source, the flag can be cleared by writing a one this location. If a DMA channel if
selected as the source, the flag is cleared when the DMA channel transaction is completed or aborted. If flash memory is
selected as the source, the flag is cleared when the CRC generation is completed.
24.7.3 DATAIN – Data Input register
 Bit 7:0 – DATAIN[7:0]: Data Input
This register is used to store the data for which the CRC checksum is computed. A new CHECKSUM is ready one clock
cycle after the DATAIN register is written.
24.7.4 CHECKSUM0 – Checksum register 0
CHECKSUM0, CHECKSUM1, CHECKSUM2, and CHECKSUM3 represent the 16- or 32-bit CHECKSUM value and the
generated CRC. The registers are reset to zero by default, but it is possible to write RESET to reset all bits to one. It is
possible to write these registers only when the CRC module is disabled. If NVM is selected as the source, reading
CHECKSUM will return a zero value until the BUSY flag is cleared. If CRC-32 is selected and the BUSY flag is cleared
(i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and
complemented result will be read from CHECKSUM. If CRC-16 is selected or the BUSY flag is set (i.e., CRC generation
is ongoing), CHECKSUM will contain the actual content.
 Bit 7:0 – CHECKSUM[7:0]: Checksum byte 0
These bits hold byte 0 of the generated CRC.
Bit 76543210
+0x02
– – – – – – ZERO BUSY
Read/Write RRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x03 DATAIN[7:0]
Read/Write WWWWWWWW
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x04 CHECKSUM[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0