Datasheet

300
XMEGA B [DATASHEET]
8291B–AVR–01/2013
24.7 Register Description
24.7.1 CTRL – Control register
 Bit 7:6 – RESET[1:0]: Reset
These bits are used to reset the CRC module, and they will always be read as zero. The CRC registers will be reset one
peripheral clock cycle after the RESET[1] bit is set
Table 24-1. CRC reset.
 Bit 5 – CRC32: CRC-32 Enable
Setting this bit will enable CRC-32 instead of the default CRC-16. It cannot be changed while the BUSY flag is set.
 Bit 4 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
 Bit 3:0 – SOURCE[3:0]: Input Source
These bits select the input source for generating the CRC. The selected source is locked until either the CRC generation
is completed or the CRC module is reset. CRC generation complete is generated and signaled from the selected source
when used with the DMA controller or flash memory.
Table 24-2. CRC source select.
Bit 76543210
+0x00 RESET[1:0] CRC32
– SOURCE[3:0]
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
RESET[1:0] Group configuration Description
00 NO No reset
01 – Reserved
10 RESET0 Reset CRC with CHECKSUM to all zeros
11 RESET1 Reset CRC with CHECKSUM to all ones
SOURCE[3:0] Group configuration Description
0000 DISABLE CRC disabled
0001 IO I/O interface
0010 FLASH Flash
0011 – Reserved for future use
0100 DMACH0 DMA controller channel 0
0101 DMACH1 DMA controller channel 1
0110 DMACH2 DMA controller channel 2
0111 DMACH3 DMA controller channel 3
1xxx – Reserved for future use