Datasheet

295
XMEGA B [DATASHEET]
8291B–AVR–01/2013
23.5.5 INTCTRL – Interrupt Control register
 Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 1:0 – INTLVL[1:0]: Interrupt priority and enable
These bits enable the AES interrupt and select the interrupt level, as described in “Interrupts and Programmable
Multilevel Interrupt Controller” on page 118. The enabled interrupt will be triggered when the SRIF in the STATUS
register is set.
Bit 7 6 5 4 3 2 1 0
+0x04
– – – – – – INTLVL[1:0]
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0