Datasheet

284
XMEGA B [DATASHEET]
8291B–AVR–01/2013
21.16 Register Summary
21.16.1 Register Description - USART
21.16.2 Register Description - USART in SPI Master Mode
21.17 Interrupt Vector Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 DATA DATA[7:0] 279
+0x01 STATUS RXCIF TXCIF DREIF FERR BUFOVF PERR – RXB8 279
+0x02 Reserved – – – – – – – –
+0x03 CTRLA – – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] 280
+0x04 CTRLB
– – – RXEN TXEN CLK2X MPCM TXB8 281
+0x05 CTRLC CMODE[1:0] PMODE[1:0] SBMODE CHSIZE[2:0] 281
+0x06 BAUDCTRL BSEL[7:0] 283
+0x07 BAUDCTRL BSCALE[3:0] BSEL[11:8] 283
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 DATA DATA[7:0] 279
+0x01 STATUS RXCIF TXCIF DREIF
– – – – – 279
+0x02 Reserved – – – – – – – –
+0x03 CTRLA – – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] 280
+0x04 CTRLB
– – – RXEN TXEN – – – 281
+0x05 CTRLC CMODE[1:0]
– – – UDORD UCPHA – 281
+0x06 BAUDCTRL BSEL[7:0] 283
+0x07 BAUDCTRL BSCALE[3:0] BSEL[11:8] 283
Offset Source Interrupt Description
0x00 RXC_vect USART receive complete interrupt vector
0x02 DRE_vect USART data register empty interrupt vector
0x04 TXC_vect USART transmit complete interrupt vector