Datasheet

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XMEGA B [DATASHEET]
8291B–AVR–01/2013
4.14.9 CTRLB – Control register B
 Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 3 – EEMAPEN: EEPROM Data Memory Mapping Enable
Setting this bit enables data memory mapping of the EEPROM section. The EEPROM can then be accessed using load
and store instructions.
 Bit 2 – FPRM: Flash Power Reduction Mode
Setting this bit enables power saving for the flash memory. If code is running from the application section, the boot loader
section will be turned off, and vice versa. If access to the section that is turned off is required, the CPU will be halted for
a time equal to the start-up time from the idle sleep mode.
 Bit 1 – EPRM: EEPROM Power Reduction Mode
Setting this bit enables power saving for the EEPROM. The EEPROM will then be turned off in a manner equivalent to
entering sleep mode. If access is required, the bus master will be halted for a time equal to the start-up time from idle
sleep mode.
 Bit 0 – SPMLOCK: SPM Locked
This bit can be written to prevent all further self-programming. The bit is cleared at reset, and cannot be cleared from
software. This bit is protected by the configuration change protection (CCP) mechanism.Refer to “Configuration Change
Protection” on page 14 for details on the CCP.
4.14.10 INTCTRL – Interrupt Control register
 Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel
Interrupt Controller” on page 121. This is a level interrupt that will be triggered only when the NVMBUSY flag in the
STATUS register is set to zero. Thus, the interrupt should not be enabled before triggering an NVM command, as the
NVMBUSY flag will not be set before the NVM command is triggered. The interrupt should be disabled in the interrupt
handler.
 Bit 1:0 – EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM ready interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 121. This is a level interrupt that will be triggered only when the
NVMBUSY flag in the STATUS register is set to zerozero. Thus, the interrupt should not be enabled before triggering an
NVM command, as the NVMBUSY flag won’t be set before the NVM command is triggered. The interrupt should be
disabled in the interrupt handler.
Bit 7 6 5 4 3 2 1 0
+0x0C
– – – – EEMAPEN FPRM EPRM SPMLOCK
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x0D
– – – – SPMLVL[1:0] EELVL[1:0]
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0