Datasheet

262
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Table 20-3. Relationship between SCK and the peripheral clock (Clk
PER
) frequency.
20.7.2 INTCTRL – Interrupt Control register
 Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 1:0 – INTLVL[1:0]: Interrupt Level
These bits enable the SPI interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel
Interrupt Controller” on page 118. The enabled interrupt will be triggered when IF in the STATUS register is set.
20.7.3 STATUS – Status register
 Bit 7 – IF: Interrupt Flag
This flag is set when a serial transfer is complete and one byte is completely shifted in/out of the DATA register. If
SS is
configured as input and is driven low when the SPI is in master mode, this will also set this flag. IF is cleared by hardware
when executing the corresponding interrupt vector. Alternatively, the IF flag can be cleared by first reading the STATUS
register when IF is set, and then accessing the DATA register.
 Bit 6 – WRCOL: Write Collision Flag
The WRCOL flag is set if the DATA register is written during a data transfer. This flag is cleared by first reading the
STATUS register when WRCOL is set, and then accessing the DATA register.
 Bit 5:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
CLK2X PRESCALER[1:0] SCK Frequency
0 00 Clk
PER
/4
0 01 Clk
PER
/16
0 10 Clk
PER
/64
0 11 Clk
PER
/128
1 00 Clk
PER
/2
1 01 Clk
PER
/8
1 10 Clk
PER
/32
1 11 Clk
PER
/64
Bit 7 6 5 4 3 2 1 0
+0x01
– – – – – – INTLVL[1:0]
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x02 IF WRCOL
– – – – – –
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0