Datasheet

257
XMEGA B [DATASHEET]
8291B–AVR–01/2013
19.11 Register Summary - TWI
19.12 Register Summary - TWI Master
19.13 Register Summary - TWI Slave
19.14 Interrupt Vector Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL – – – – – SDAHOLD[1:0] EDIEN 246
+0x01 MASTER Offset address for TWI Master
+0x08 SLAVE Offset address for TWI Slave
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA INTLVL[1:0] RIEN WIEN ENABLE – – – 247
+0x01 CTRLB – – – – TIMEOUT[1:0] QCEN SMEN 247
+0x02 CTRLC – – – – – ACKACT CMD[1:0] 248
+0x03 STATUS RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[1:0] 249
+0x04 BAUD BAUD[7:0] 250
+0x05 ADDR ADDR[7:0] 251
+0x06 DATA DATA[7:0] 251
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA INTLVL[1:0] DIEN APIEN ENABLE PIEN TPMEN SMEN 252
+0x01 CTRLB – – – – – ACKACT CMD[1:0] 252
+0x02 STATUS DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP 254
+0x03 ADDR ADDR[7:0] 255
+0x04 DATA DATA[7:0] 255
+0x05 ADDRMAS ADDRMASK[7:1] ADDREN 256
Offset Source Interrupt Description
0x00 SLAVE_vect TWI slave interrupt vector
0x02 MASTER_vect TWI master interrupt vector