Datasheet

256
XMEGA B [DATASHEET]
8291B–AVR–01/2013
19.10.6 ADDRMASK – Address Mask register
 Bit 7:1 – ADDRMASK[7:1]: Address Mask
These bits can act as a second address match register or as an address mask register, depending on the ADDREN
setting.
If ADDREN is set to zero, ADDRMASK can be loaded with a 7-bit slave address mask. Each bit in ADDRMASK can
mask (disable) the corresponding address bit in the ADDR register. If the mask bit is one, the address match between the
incoming address bit and the corresponding bit in ADDR is ignored; i.e., masked bits will always match.
If ADDREN is set to one, ADDRMASK can be loaded with a second slave address in addition to the ADDR register. In
this mode, the slave will match on two unique addresses, one in ADDR and the other in ADDRMASK.
 Bit 0 – ADDREN: Address Enable
By default, this bit is zero, and the ADDRMASK bits acts as an address mask to the ADDR register. If this bit is set to
one, the slave address match logic responds to the two unique addresses in ADDR and ADDRMASK.
Bit 7 6 5 4 3 2 1 0
+0x05 ADDRMASK[7:1] ADDREN
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0