Datasheet

248
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Table 19-3. TWI master inactive bus timeout settings.
 Bit 1 – QCEN: Quick Command Enable
When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the
address (read or write interrupt). At this point, software can issue either a STOP or a repeated START condition.
 Bit 0 – SMEN: Smart Mode Enable
Setting this bit enables smart mode. When smart mode is enabled, the acknowledge action, as set by the ACKACT bit in
the CTRLC register, is sent immediately after reading the DATA register.
19.9.3 CTRLC – Control register C
 Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2 – ACKACT: Acknowledge Action
This bit defines the master's acknowledge behavior in master read mode. The acknowledge action is executed when a
command is written to the CMD bits. If SMEN in the CTRLB register is set, the acknowledge action is performed when
the DATA register is read.
Table 19-4 lists the acknowledge actions.
Table 19-4. ACKACT bit description.
 Bit 1:0 – CMD[1:0]: Command
Writing the command (CMD) bits triggers a master operation as defined by Table 19-5. The CMD bits are strobe bits, and
always read as zero. The acknowledge action is only valid in master read mode (R). In master write mode (
W), a
command will only result in a repeated START or STOP condition. The ACKACT bit and the CMD bits can be written at
the same time, and then the acknowledge action will be updated before the command is triggered.
TIMEOUT[1:0] Group Configuration Description
00 DISABLED Disabled, normally used for I
2
C
01 50US 50μs, normally used for SMBus at 100kHz
10 100US 100μs
11 200US 200μs
Bit 76543210
+0x02
– – – – – ACKACT CMD[1:0]
Read/Write R RRRRR/WR/WR/W
Initial Value 00000000
ACKACT Action
0 Send ACK
1 Send NACK