Datasheet

245
XMEGA B [DATASHEET]
8291B–AVR–01/2013
19.6.1 Receiving Address Packets
When the TWI slave is properly configured, it will wait for a START condition to be detected. When this happens, the
successive address byte will be received and checked by the address match logic, and the slave will ACK a correct
address and store the address in the DATA register. If the received address is not a match, the slave will not
acknowledge and store address, and will wait for a new START condition.
The slave address/stop interrupt flag is set when a START condition succeeded by a valid address byte is detected. A
general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition is an illegal operation, and the bus error flag is set.
The R/
W direction flag reflects the direction bit received with the address. This can be read by software to determine the
type of operation currently in progress.
Depending on the R/
W direction bit and bus condition, one of four distinct cases (S1 to S4) arises following the address
packet. The different cases must be handled in software.
19.6.1.1 Case S1: Address packet accepted - Direction bit set
If the R/
W direction flag is set, this indicates a master read operation. The SCL line is forced low by the slave, stretching
the bus clock. If ACK is sent by the slave, the slave hardware will set the data interrupt flag indicating data is needed for
transmit. Data, repeated START, or STOP can be received after this. If NACK is sent by the slave, the slave will wait for
a new START condition and address match.
19.6.1.2 Case S2: Address packet accepted - Direction bit cleared
If the R/
W direction flag is cleared, this indicates a master write operation. The SCL line is forced low, stretching the bus
clock. If ACK is sent by the slave, the slave will wait for data to be received. Data, repeated START, or STOP can be
received after this. If NACK is sent, the slave will wait for a new START condition and address match.
19.6.1.3 Case S3: Collision
If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the data and acknowledge
output from the slave logic. The clock hold is released. A START or repeated START condition will be accepted.
19.6.1.4 Case S4: STOP condition received.
When the STOP condition is received, the slave address/stop flag will be set, indicating that a STOP condition, and not
an address match, occurred.
19.6.2 Receiving Data Packets
The slave will know when an address packet with R/W direction bit cleared has been successfully received. After
acknowledging this, the slave must be ready to receive data. When a data packet is received, the data interrupt flag is set
and the slave must indicate ACK or NACK. After indicating a NACK, the slave must expect a STOP or repeated START
condition.
19.6.3 Transmitting Data Packets
The slave will know when an address packet with R/W direction bit set has been successfully received. It can then start
sending data by writing to the slave data register. When a data packet transmission is completed, the data interrupt flag
is set. If the master indicates NACK, the slave must stop transmitting data and expect a STOP or repeated START
condition.
19.7 Enabling External Driver Interface
An external driver interface can be enabled. When this is done, the internal TWI drivers with input filtering and slew rate
control are bypassed. The normal I/O pin function is used, and the direction must be configured by the user software.
When this mode is enabled, an external TWI compliant tri-state driver is needed for connecting to a TWI bus.
By default, port pins 0 (Pn0) and 1 (Pn1) are used for SDA and SCL. The external driver interface uses port pins 0 to 3 for
the SDA_IN, SCL_IN, SDA_OUT, and SCL_OUT signals.