Datasheet

234
XMEGA B [DATASHEET]
8291B–AVR–01/2013
18.16 Register Summary – USB Module
18.17 Register Summary – USB Endpoint
The address to the first configuration byte is (EPPTR[15:0] + 16 × endpoint address) for OUT endpoints and
(EPPTR[15:0] + 16 × endpoint address + 8) for IN endpoints.
18.18 Register Summary – Frame
The address to the frame configuration byte is (MAXEP + 1) << 4. For instance with MAXEP = 3, the first address would
be located at offset address 0x40.
18.19 USB Interrupt Vector Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA ENABLE SPEED FIFOEN STFRNUM MAXEP[3:0] 221
+0x01 CTRLB – – – PULLRST – RWAKEUP GNACK ATTACH 221
+0x02 STATUS – – – – UPRESUM RESUME SUSPEND BUSRST 222
+0x03 ADDR – ADDR[6:0] 222
+0x04 FIFOWP – – – FIFOWP[4:0] 223
+0x05 FIFORP – – – FIFORP[4:0] 223
+0x06 EPPTRL EPPTR[7:0] 223
+0x07 EPPTRH EPPTR[15:8] 224
+0x08 INTCTRLA SOFIE BUSEVIE BUSERRIE STALLIE – – INTLVL[1:0] 224
+0x09 INTCTRLB – – – – – – TRNIE SETUPIE 225
+0x0A INFLAGSACL SOFIF SUSPENDI RESUMEIF RSTIF CRCIF UNFIF OVFIF STALLIF 225
+0x0B INFLAGSASE SOFIF SUSPENDI RESUMEIF RSTIF CRCIF UNFIF OVFIF STALLIF 225
+0x0C INFLAGSBCL – – – – – – TRNIF SETUPIF 226
+0x0D INFLAGSBSE – – – – – – TRNIF SETUPIF 226
+0x0E Reserved – – – – – – – –
+0x0F Reserved – – – – – – – –
+0x10-0X39 Reserved – – – – – – – –
+0x3A CALL CAL[7:0] 226
+0x3B CALH CAL[15:8] 227
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 STATUS STALL OVF/UNF TRNCOMP
L0
SETUP BANK BUSNACK1 BUSNACK0 TOGGLE 228
CRC TRNCOMP Isochronous
+0x01 CTRL TYPE[1:0] MULTIPKT PINGPONG INTDSB
L
STALL BUFSIZE[1:0] 229
BUFSIZE[2:0] Isochronous
+0x02 CNTL CNT[7:0] 230
+0x03 CNTH AZLP – – – – – CNT[9:8] 231
+0x04 DATAPTR DATAPTR[7:0] 231
+0x05 DATAPTR DATAPTR[15:8] 231
+0x06 AUXDATA AUXDATA[7:0] 232
+0x07 AUXDATA AUXDATA[15:8] 232
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 FRAMENUM FRAMENUM[7:0] 233
+0x01 FRAMENUM FRAMEER – – – – FRAMENUM[10:8] 233
Offset Source Interrupt Description
0x00 BUSEVENT_vect SOF, suspend, resume, bus reset, CRC, underflow, overflow, and stall error interrupts
0x02 TRNCOMPL_vect Transaction complete interrupt