Datasheet

225
XMEGA B [DATASHEET]
8291B–AVR–01/2013
 Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 1:0 – INTLVL[1:0]: Interrupt Level
These bits enable the USB interrupts and select the interrupt level, as described in “Interrupts and Programmable
Multilevel Interrupt Controller” on page 118. In addition, each USB interrupt source must be separately enabled.
18.13.10INTCTRLB – Interrupt Control register B
 Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 1 – TRNIE: Transaction Complete Interrupt Enable
Setting this bit enables the transaction complete interrupt for IN and OUT transactions. The INTLVL bits must be nonzero
for interrupts to be generated.
 Bit 0 – SETUPIE: SETUP Transaction Complete Interrupt Enable
Setting this bit enables the SETUP Transaction Complete Interrupt for SETUP transactions. The INTLVL bits must be
non-zero for the interrupts to be generated.
18.13.11INTFLAGSACLR/ INTFLAGSASET – Clear/ Set Interrupt Flag register A
This register is mapped into two I/O memory locations, one for clearing (INTFLAGSACLR) and one for setting
(INTFLAGSASET) the flags. The individual flags can be set by writing a one to their bit locations in INFLAGSASET, and
cleared by writing a one to their bit locations in INT-FLAGSACLR. Both memory locations will provide the same result
when read, and writing zero to any bit location has no effect.
 Bit 7 – SOFIF: Start Of Frame Interrupt Flag
This flag is set when a start of frame packet has been received.
 Bit 6 – SUSPENDIF: Suspend Interrupt Flag
This flag is set when the bus has been idle for 3ms.
 Bit 5 – RESUMEIF: Resume Interrupt Flag
This flag is set when a non-idle state has been detected on the bus while the USB module is in the suspend state. This
interrupt is asynchronous, and is able to wake the CPU from sleep modes where the system clock is stopped, such as
power-down and power-save sleep modes.
 Bit 4 – RSTIF: Reset Interrupt Flag
This flag is set when a reset condition has been detected on the bus.
Bit 765432 1 0
+0x07
– – – – – – TRNIE SETUPIE
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0A/ +0x0B SOFIF SUSPENDIF RESUMEIF RESETIF CRCIF UNFIF OVFIF STALLIF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0