Datasheet

224
XMEGA B [DATASHEET]
8291B–AVR–01/2013
18.13.8 EPPTRH – Endpoint Configuration Table Pointer High
 Bit 7:0 – EPPTR[15:8]: Endpoint Configuration Table Pointer high byte
This register contains the eight msbs of the endpoint configuration table pointer (EPPTR).
18.13.9 INTCTRLA – Interrupt Control register A
 Bit 7 – SOFIE: Start Of Frame Interrupt Enable
Setting this bit enables the start of frame (SOF) interrupt for the conditions that set the start of frame interrupt flag
(SOFIF) in the INTFLAGSACLR/ INTFLAGSASET register. The INTLVL bits must be nonzero for the interrupts to be
generated.
 Bit 6 – BUSEVIE: Bus Event Interrupt Enable
Setting this bit will enable the interrupt for the following three bus events:
1. Suspend: An interrupt will be generated for the conditions that set the suspend interrupt flag (SUSPENDIF) in the
INTFLAGSACLR/SET register.
2. Resume: An interrupt will be generated for the conditions that set the resume interrupt flag (RESUMEIF) in the
INTFLAGSACLR/SET register.
3. Reset: An interrupt will be generated for the conditions that set the reset interrupt flag (RESETIF) in the INTFLAG-
SACLR/SET register.
The INTLVL bits must be nonzero for the interrupts to be generated.
 Bit 5 – BUSERRIE: Bus Error Interrupt Enable
Setting this bit will enable the interrupt for the following three bus error events:
1. Isochronous CRC Error: An interrupt will be generated for the conditions that set the CRC interrupt flag (CRCIF) in
the INTFLAGSACLR/SET register during isochronous transfers.
2. Underflow: An interrupt will be generated for the conditions that set the undeflow interrupt flag (UNFIF) in the
INTFLAGSACLR/SET register.
3. Overflow: An interrupt will be generated for the conditions that set the overflow interrupt flag (OVFIF) in the
INTFLAGSACLR/SET register.
The INTLVL bits must be nonzero for the interrupts to be generated.
 Bit 4 – STALLIE: STALL Interrupt Enable
Setting this bit enables the STALL interrupt for the conditions that set the stall interrupt flag (STALLIF) in the
INTFLAGSACLR/SET register. The INTLVL bits must be nonzero for the interrupts to be generated.
Bit 76543210
+0x07 EPPTR[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x06 SOFIE BUSEVIE BUSERRIE STALLIE
– – INTLVL[1:0]
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0