Datasheet

205
XMEGA B [DATASHEET]
8291B–AVR–01/2013
17.3.5 TEMP – Temporary register
 Bit 7:0 – TEMP[7:0]: Temporary bits
This register is used for 16-bit access to the counter value, compare value, and TOP value registers. The low byte of the
16-bit register is stored here when it is written by the CPU. The high byte of the 16-bit register is stored when the low byte
is read by the CPU. For more details, refer to “Accessing 16-bit Registers” on page 13.
17.3.6 CNTL – Counter register Low
The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT counts positive clock edges on the prescaled
RTC clock. Reading and writing 16-bit values requires special attention. Refer to “Accessing 16-bit Registers” on page 13
for details.
Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles
from updating the register until this has an effect. Application software needs to check that the SYNCBUSY flag in the
“STATUS – Status register” on page 203 is cleared before writing to this register.
 Bit 7:0 – CNT[7:0]: Counter Value low byte
These bits hold the LSB of the 16-bit real-time counter value.
17.3.7 CNTH – Counter Register High
 Bit 7:0 – CNT[15:8]: Counter Value high byte
These bits hold the MSB of the 16-bit real-time counter value.
Bit 76543210
+0x04 TEMP[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x08 CNT[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 000000
Bit 76543210
+0x09 CNT[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0