Datasheet

203
XMEGA B [DATASHEET]
8291B–AVR–01/2013
17.3 Register Descriptions
17.3.1 CTRL – Control register
 Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2:0 – PRESCALER[2:0]: Clock Prescaling factor
These bits define the prescaling factor for the RTC clock according to Table 17-1.
Table 17-1. Real-time counter clock prescaling factor.
17.3.2 STATUS – Status register
 Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set when the CNT, CTRL, PER, or COMP register is busy synchronizing between the RTC clock and system
clock domains. THis flag is automatically cleared when the synchronisation is complete
Bit 76543210
+0x00
– – – – – PRESCALER[2:0]
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
PRESCALER[2:0] Group Configuration RTC Clock Prescaling
000 OFF No clock source, RTC stopped
001 DIV1 RTC clock / 1 (no prescaling)
010 DIV2 RTC clock / 2
011 DIV8 RTC clock / 8
100 DIV16 RTC clock / 16
101 DIV64 RTC clock / 64
110 DIV256 RTC clock / 256
111 DIV1024 RTC clock / 1024
Bit 7654321 0
+0x01
– – – – – – – SYNCBUSY
Read/Write RRRRRRR R
Initial Value 0 0 0 0 0 0 0 0