Datasheet

197
XMEGA B [DATASHEET]
8291B–AVR–01/2013
15.7.7 DTLS – Dead-time Low Side register
 Bit 7:0 – DTLS: Dead-time Low Side
This register holds the number of peripheral clock cycles for the dead-time low side.
15.7.8 DTHS – Dead-time High Side register
 Bit 7:0 – DTHS: Dead-time High Side
This register holds the number of peripheral clock cycles for the dead-time high side.
15.7.9 DTLSBUF – Dead-time Low Side Buffer register
 Bit 7:0 – DTLSBUF: Dead-time Low Side Buffer
This register is the buffer for the DTLS register. If double buffering is used, valid content in this register is copied to the
DTLS register on an UPDATE condition.
15.7.10 DTHSBUF – Dead-time High Side Buffer register
 Bit 7:0 – DTHSBUF: Dead-time High Side Buffer
This register is the buffer for the DTHS register. If double buffering is used, valid content in this register is copied to the
DTHS register on an UPDATE condition.
Bit 76543210
+0x08 DTLS[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x09 DTHS[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x0A DTLSBUF[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
+0x0B DTHSBUF[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000