Datasheet

196
XMEGA B [DATASHEET]
8291B–AVR–01/2013
15.7.4 STATUS – Status register
 Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2 – FDF: Fault Detect Flag
This flag is set when a fault detect condition is detected; i.e., when an event is detected on one of the event channels
enabled by FDEVMASK. This flag is cleared by writing a one to its bit location.
 Bit 1 – DTHSBUFV: Dead-time High Side Buffer Valid
If this bit is set, the corresponding DT buffer is written and contains valid data that will be copied into the DTLS register on
the next UPDATE condition. If this bit is zero, no action will be taken. The connected timer/counter unit’s lock update
(LUPD) flag also affects the update for dead-time buffers.
 Bit 0 – DTLSBUFV: Dead-time Low Side Buffer Valid
If this bit is set, the corresponding DT buffer is written and contains valid data that will be copied into the DTHS register
on the next UPDATE condition. If this bit is zero, no action will be taken. The connected timer/counter unit's lock update
(LUPD) flag also affects the update for dead-time buffers.
15.7.5 DTBOTH – Dead-time Concurrent Write to Both Sides
 Bit 7:0 – DTBOTH: Dead-time Both Sides
Writing to this register will update the DTHS and DTLS registers at the same time (i.e., at the same I/O write access).
15.7.6 DTBOTHBUF – Dead-time Concurrent Write to Both Sides Buffer register
 Bit 7:0 – DTBOTHBUF: Dead-time Both Sides Buffer
Writing to this memory location will update the DTHSBUF and DTLSBUF registers at the same time (i.e., at the same I/O
write access).
Bit 76543 2 1 0
+0x04
– – – – – FDF DTHSBUFV DTLSBUFV
Read/Write R R R R R R/W R/W R/W
Initial Value 00000 0 0 0
Bit 76543210
+0x06 DTBOTH[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
+0x07 DTBOTHBUF[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000