Datasheet

194
XMEGA B [DATASHEET]
8291B–AVR–01/2013
15.7 Register Description
15.7.1 CTRL – Control register
 Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 5 – PGM: Pattern Generation Mode
Setting this bit enables the pattern generation mode. This will override the DTI, and the pattern generation reuses the
dead-time registers for storing the pattern.
 Bit 4 – CWCM: Common Waveform Channel Mode
If this bit is set, the CC channel A waveform output will be used as input for all the dead-time generators. CC channel B,
C, and D waveforms will be ignored.
 Bit 3:0 – DTICCxEN: Dead-Time Insertion CCx Enable
Setting these bits enables the dead-time generator for the corresponding CC channel. This will override the timer/counter
waveform outputs.
15.7.2 FDEMASK – Fault Detect Event Mask register
 Bit 7:0 – FDEVMASK[7:0]: Fault Detect Event Mask
These bits enable the corresponding event channel as a fault condition input source. Events from all event channels will
be ORed together, allowing multiple sources to be used for fault detection at the same time. When a fault is detected, the
fault detect flag (FDF) is set and the fault detect action (FDACT) will be performed.
Bit 7 6 5 4 3 2 1 0
+0x00
– – PGM CWCM DTICCDEN DTICCCEN DTICCBEN DTICCAEN
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x02 FDEVMASK[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 000000