Datasheet

171
XMEGA B [DATASHEET]
8291B–AVR–01/2013
13.12.11TEMP – Temporary bits for 16-bit Access
The TEMP register is used for single-cycle, 16-bit access to the 16-bit timer/counter registers by the CPU. The DMA
controller has a separate temporary storage register. There is one common TEMP register for all the 16-bit Timer/counter
registers.
For more details, refer to “Accessing 16-bit Registers” on page 13.
13.12.12CNTL – Counter register Low
The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the
timer/counter. CPU and DMA write access has priority over count, clear, or reload of the counter.
For more details on reading and writing 16-bit registers, refer to “Accessing 16-bit Registers” on page 13.
 Bit 7:0 – CNT[7:0]: Counter low byte
These bits hold the LSB of the 16-bit counter register.
13.12.13CNTH – Counter register High
 Bit 7:0 – CNT[15:8]: Counter high byte
These bits hold the MSB of the 16-bit counter register.
13.12.14PERL – Period register Low
The PERH and PERL register pair represents the 16-bit value, PER. PER contains the 16-bit TOP value in the
timer/counter.
 Bit 7:0 – PER[7:0]: Period low byte
These bits hold the LSB of the 16-bit period register.
Bit 76543210
+0x0F TEMP[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 00000
Bit 7 6 5 4 3 2 1 0
+0x20 CNT[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x21 CNT[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
+0x26 PER[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 1 1 111111