Datasheet

162
XMEGA B [DATASHEET]
8291B–AVR–01/2013
where N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the
peripheral clock frequency (fclk
PER
) when CCA is set to zero (0x0000) and no prescaling is used. This also applies when
using the hi-res extension, since this increases the resolution and not the frequency.
13.8.4 Dual-slope PWM
For dual-slope PWM generation, the period (T) is controlled by PER, while CCx registers control the duty cycle of the WG
output. Figure 13-16 shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOP and then from
TOP to BOTTOM. The waveform generator output is set on BOTTOM, cleared on compare match when up-counting,
and set on compare match when down-counting.
Figure 13-16.Dual-slope pulse width modulation.
Using dual-slope PWM results in a lower maximum operation frequency compared to the single-slope PWM operation.
The period register (PER) defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the
maximum resolution is 16 bits (PER=MAX).
The following equation calculate the exact resolution for dual-slope PWM (R
PWM_DS
):
The PWM frequency depends on the period setting (PER) and the peripheral clock frequency (fclk
PER
), and can be
calculated by the following equation:
N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the
peripheral clock frequency (fclk
PER
) when CCA is set to zero (0x0000) and no prescaling is used. This also applies when
using the hi-res extension, since this increases the resolution and not the frequency.
13.8.5 Port Override for Waveform Generation
To make the waveform generation available on the port pins, the corresponding port pin direction must be set as output.
The timer/counter will override the port pin values when the CC channel is enabled (CCENx) and a waveform generation
mode is selected.
f
PWM_SS
fclk
PER
N PER 1+
------------------------------
=
CNT
MAX
TOP
Period (T)
BOTTOM
WG Output
CCx=BOTTOM
CCx
CCx=TOP
"match"
"update"
R
PWM_DS
PER 1+log
2log
---------------------------------
=
f
PWM_DS
fclk
PER
2NPER
--------------------
=