Datasheet

141
XMEGA B [DATASHEET]
8291B–AVR–01/2013
12.12.15PINnCTRL – Pin n Configuration Register
 Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
 Bit 6 – INVEN: Inverted I/O Enable
Setting this bit will enable inverted output and input data on pin n.
 Bit 5:3 – OPC: Output and Pull Configuration
These bits set the output/pull configuration on pin n according to Table 12-5.
Table 12-5. Output/pull configuration
 Bit 2:0 – ISC[2:0]: Input/Sense Configuration
These bits set the input and sense configuration on pin n according to Table 12-6 on page 141. The sense configuration
decides how the pin can trigger port interrupts and events. If the input buffer is not disabled, the input cannot be read in
the IN register.
Table 12-6. Input/sense configuration.
Bit 76543210
– INVEN OPC[2:0] ISC[2:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
OPC[2:0] Group Configuration
Description
Output Configuration Pull Configuration
000 TOTEM Totem-pole (N/A)
001 BUSKEEPER Totem-pole Bus-keeper
010 PULLDOWN Totem-pole Pull-down (on input)
011 PULLUP Totem-pole Pull-up (on input)
100 WIREDOR Wired-OR (N/A)
101 WIREDAND Wired-AND (N/A)
110 WIREDORPULL Wired-OR Pull-down
111 WIREDANDPULL Wired-AND Pull-up
ISC[2:0] Group Configuration Description
000 BOTHEDGES Sense both edges
001 RISING Sense rising edge
010 FALLING Sense falling edge
011 LEVEL Sense low level
(1)