Datasheet

127
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 12-1. General I/O pin functionality.
12.3 I/O Pin Use and Configuration
Each port has one data direction (DIR) register and one data output value (OUT) register that are used for port pin
control. The data input value (IN) register is used for reading the port pins. In addition, each pin has a pin configuration
(PINnCTRL) register for additional pin configuration.
Direction of the pin is decided by the DIRn bit in the DIR register. If DIRn is written to one, pin n is configured as an output
pin. If DIRn is written to zero, pin n is configured as an input pin.
When direction is set as output, the OUTn bit in OUT is used to set the value of the pin. If OUTn is written to one, pin n is
driven high. If OUTn is written to zero, pin n is driven low.
The IN register is used for reading pin values. A pin value can always be read regardless of whether the pin is configured
as input or output, except if digital input is disabled.
The I/O pins are tri-stated when a reset condition becomes active, even if no clocks are running.
The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole,
wired-AND, or wired-OR configuration. It is also possible to enable inverted input and output for a pin.
A totem-pole output has four possible pull configurations: totem-pole (push-pull), pull-down, pull-up, and bus-keeper. The
bus-keeper is active in both directions. This is to avoid oscillation when disabling the output. The totem-pole
D
Q
R
D
Q
R
Synchronizer
D
Q
R
D
Q
R
DIRn
OUTn
PINnCTRL
INn
Pxn
D
Q
R
C
o
n
t
r
o
l
L
o
g
i
c
Input Disable
Wired AND/OR
Digital Input Pin
Analog Input/Output
Inverted I/O
Pull Enable
Pull Keep
Pull Direction