Datasheet

125
XMEGA B [DATASHEET]
8291B–AVR–01/2013
11.8.3 CTRL – Control register
 Bit 7 – RREN: Round-robin Scheduling Enable
When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts. When this bit is cleared,
the priority is static according to interrupt vector address, where the lowest address has the highest priority.
 Bit 6 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the application section in flash. When
this bit is set (one), the interrupt vectors are placed in the beginning of the boot section of the flash. Refer to the device
datasheet for the absolute address.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on
page 13 for details.
 Bit 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2 – HILVLEN: High-level Interrupt Enable
(1)
When this bit is set, all high-level interrupts are enabled. If this bit is cleared, high-level interrupt requests will be ignored.
 Bit 1 – MEDLVLEN: Medium-level Interrupt Enable
(1)
When this bit is set, all medium-level interrupts are enabled. If this bit is cleared, medium-level interrupt requests will be
ignored.
 Bit 0 – LOLVLEN: Low-level Interrupt Enable
(1)
When this bit is set, all low-level interrupts are enabled. If this bit is cleared, low-level interrupt requests will be ignored.
Note: 1. Ignoring interrupts will be effective one cycle after the bit is cleared.
11.9 Register Summary
Bit 765432 1 0
+0x02 RREN IVSEL
– – – HILVLEN MEDLVLEN LOLVLEN
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value 0 00000 0 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 STATUS NMIEX – – – – HILVLEX MEDLVLEX LOLVLEX 124
+0x01 INTPRI INTPRI[7:0] 124
+0x02 CTRL RREN IVSEL – – – HILVLEN MEDLVLEN LOLVLEN 125