Datasheet

110
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 9-6. Watchdog reset.
For information on configuration and use of the WDT, refer to the “WDT – Watchdog Timer” on page 113.
9.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
Figure 9-7. Software reset.
9.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
1-2 2MHz
CC
Cycles
1-2 2MHz
CC
Cycles
SOFTWARE